1. Field of the Invention
The present invention generally relates to an information processing method and an information processing apparatus. More specifically, the present invention is directed to such an information processing method/apparatus capable of increasing a throughput of this information processing apparatus equipped with a CPU, a memory, a plurality of input/output(I/O) devices, a direct memory access controller (DMAC), and at least two buses, while effectively utilizing these buses.
2. Description of the Related Art
Conventionally, information processing apparatuses are known in the technical field. For instance, one conventional information processing apparatus as described in Japanese Patent Laid-open Application No. Hei5-274250 published in 1993 is schematically shown in FIG. 27.
This conventional information processing apparatus is mainly arranged by the one-chip microcomputer 1, the direct memory access controller (DMAC) 2, the input/output (I/O) device 3, and the external memory 4. These structural elements are connected via the external bus 5 to each other. This one-chip microcomputer 1 is constructed in such a manner that the central processing unit (CPU) 6, the internal memory 7, the bus arbiter 8, and the internal (data) bus 9 are manufactured on a single semiconductor chip. The CPU 6, the internal memory 7, and the bus arbiter 8 are connected via the internal bus 9 to each other. The CPU 6 contains the bus controller 10 for controlling the connection/disconnection between the internal bus 9 and the CPU 6. The bus controller 10 enters therein to the request signal from the bus arbiter 8, and supplies the acknowledge signal to this bus arbiter 8. This request signal indicates that the bus arbiter 8 requests to release the internal bus 9. The acknowledge signal indicates that the bus arbiter 8 is allowed to release the internal bus 9.
The bus arbiter 8 is connected with the internal bus 9 and the external bus 5. The external request for requesting releasing of both the external bus 5 and the internal bus 9 is inputted from the DMAC 2 into this bus arbiter 8. Also, this bus arbiter 8 supplies the external acknowledge signal for allowing releasing of both the external bus 5 and the internal bus 9 to the DMAC 2. The bus arbiter 8 may release only the external bus 5 while isolating the connection between the internal bus 9 and the external bus 5 with respect to the DMAC 2 in response to the state of the mode selection bit 11. Also, the bus arbiter 8 may release any of the internal bus 9 and the external bus 5 under such a condition that the external bus 5 is connected to the internal bus 9. The state of the mode selection bit 11 is rewritable in accordance with the programs supplied from the CPU 6 and the DMAC 2. The bus arbiter 8 supplies the retry signal to the bus controller 10 of the CPU 6. This retry signal is used to retry the bus cycle of the CPU 6 while the DMAC 2 occupies the external bus 5, and the data transfer to the I/O device 3 or the external memory 4 is set to write state.
With employment of such an arrangement, in the conventional information processing apparatus, even when the program is being executed, the bus arbiter causes the operating states of the DMAC 2 to be transferred by rewriting the mode selection bit 11 and also supplying the external request signal from the DMAC 2 to the bus arbiter 8. As a result, both the CPU 6 and the DMAC 2 can use their data buses in parallel, so that the operating rate of the CPU 6 is increased and therefore the overall throughput is increased. These operating states contain the first to third states. In the first state, none of the external bus 5 and the internal bus 9 is released. In the second state, while the external bus 5 and the internal bus 9 are connected, any one of these data buses is released. In the third state, only the external bus 5 is released. The bus arbiter 8 transfers the first state into the second state, or the third state. The bus arbiter 8 transfers either the second state or the third state into the first state. Otherwise, the bus arbiter 8 transfers the second state into the third state.
In the above-described conventional information processing apparatus, under the third condition where the bus arbiter 8 disconnects the connection between the external bus 5 and the internal bus 9, the CPU 6 and the DMAC 2 can use the internal bus 9 and the external bus 5 respectively inside and also outside the one-chip microcomputer 1.
However, under the first state and the second state where the bus arbiter 8 connects the external bus 5 in series to the internal bus 9, either the CPU 6 or the DMAC 2 occupies both the external bus 5 and the internal bus 9 at the same time. As a consequence, the following simultaneous process operations cannot be carried out. For example, while the CPU 6 reads the data stored in the external memory 4, the DMAC 2 transfers the data stored in the internal memory 7 to the I/O device 3.
In such a case, either the CPU 6 or the DMAC 2 must interrupt the above-described process operations.
As a result, the conventional information has such a drawback. That is, there is a limitation in increasing of the operating rate of this CPU 6, namely improvement in the throughput of the overall conventional information processing apparatus. This drawback could not be solved even when all of the structural elements shown in FIG. 27 are manufactured in an one-chip structure as disclosed in the above-described Japanese Patent Laid-open Application.